 module trans(c_in,clock_1);
input c_in;
output reg clock_1;
integer i;
always@ (posedge c_in)
begin
if(i==2800000) begin clock_1<=~clock_1; i<=0;end
else i<=i+1;
end
endmodule
module div_clock_1hz(clock_in,clock_out);
input clock_in;
output reg clock_out;
integer i;
always @(posedge clock_in)
begin
if(i==25000000) begin clock_out<=~clock_out; i<=0;end
else i<=i+1;
end
endmodule
